A unified approach for the synthesis of self-testable finite state machines

Conventionally self-test hardware is added after synthesis is completed. For highly sequential circuits like controllers this design method either leads to high hardware overheads or compromises fault coverage. In this paper we outline a unified approach for considering self-test hardware like pattern generators and signature registers during synthesis. Three novel target structures are presented, and a method for designing parallel self-testable circuits is discussed in more detail. For a collection of benchmark circuits we show that hardware overheads for self-testable circuits can be significantly reduced this way without sacrificing testability

Optimized synthesis of self-testable finite state machines

A synthesis procedure for self-testable finite state machines is presented. Testability comes under consideration when the behavioral description of the circuit is being transformed into a structural description. To this end, a novel state encoding algorithm, as well as a modified self-test architecture, is developed. Experimental results show that this approach leads to a significant reduction of hardware overhead. Self-testing circuits generally employ linear feedback shift registers for pattern generation. The impact of choosing a particular feedback polynomial on the state encoding is discussed

A Unified Approach for the Synthesis of Self-Testable Finite State

Abstract- Conventionally self-test hardware is added after synthesis is completed. For highly sequential circuits like controllers this design method either leads to high hardware overheads or compromises fault coverage. In this paper we outline a unified approach for considering self-test hardware like pattern generators and signature registers during synthe-sis. Three novel target structures are presented, and a method for designing parallel self-testable circuits is discussed in more detail. For a collection of benchmark circuits we show that hardware overheads for self-testable circuits can be significantly reduced this way without sacrificing testability.

Optimized Synthesis Techniques for Testable Sequential Circuits; in

Abstract-Innovative synthesis for testability strategies aim at considering testability while synthesizing a circuit, whereas conventional design for testability methods modify the design after the circuit structure is synthesized. We describe a synthe-sis approach that maps a behavioral FSM description into a testable gate-level structure. The term “testable ” in this con-text, besides implying the existence of tests, also means that the application of test patterns is facilitated. Depending on the test strategy, the state registers of the FSM are modified e.g. as scan path or self-test registers. The additional functionality of these state registers is utilized in system mode by interpreting them as “smart ” state registers, capable of producing certain state transitions on their own. To make the best use of such registers, we propose a novel state encoding strategy based on an analytic formulation of the coding constraint satisfaction problem as a quadratic assignment problem. An additional minimization potential can be exploited by appropriately choosing the pattern generator for self-testable designs. Exper-imental results indicate that, compared with conventional de-sign for testability approaches, significant savings are possible this way. I

Complementary Metal Oxide Semiconductor Compatible Silicon Nanowires-on-a-Chip: Fabrication and Preclinical Validation for the Detection of a Cancer Prognostic Protein Marker in Serum

An integrated translational biosensing technology based on arrays of silicon nanowire field-effect transistors (SiNW FETs) is described and has been preclinically validated for the ultrasensitive detection of the cancer biomarker ALCAM in serum. High-quality SiNW arrays have been rationally designed toward their implementation as molecular biosensors. The FET sensing platform has been fabricated using a complementary metal oxide semiconductor (CMOS)-compatible process. Reliable and reproducible electrical performance has been demonstrated via electrical characterization using a custom-designed portable readout device. Using this platform, the cancer prognostic marker ALCAM could be detected in serum with a detection limit of 15.5 pg/mL. Importantly, the detection could be completed in less than 30 min and span a wide dynamic detection range (∼105). The SiNW-on-a-chip biosensing technology paves the way to the translational clinical application of FET in the detection of cancer protein markers